/**
 * ALU module.
 **/
module Alu(op, operand1, operand2, result);
   input wire [3:0] op;
   input wire [31:0] operand1;
   input wire [31:0] operand2;
   output wire [32:0] result;
   reg [32:0]         res;
   always @ (op or operand1 or operand2)
     case (op)
       4'b0000: res = operand1 + operand2;
       4'b0001: res = operand1 - operand2;
       4'b0010: res = {1'b0, operand1[31:16], operand2[15:0]};
       4'b0011: res = {1'b0, operand2[15:0], operand1[15:0]};
     endcase // case (op)
   assign result = res;
endmodule
